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Vdhl Modeling for Digital Design Synthesis by Eric S. Lin, Jessie T. Liu, Kevin F. Tsai, Yu-Chin Hsu (1995, Hardcover) 
Vdhl Modeling for Digital Design Synthesis by Eric S. Lin, Jessie T. Liu, Kevin F. Tsai, Yu-Chin Hsu (1995, Hardcover)
Author: Eric S. Lin, Jessie T. Liu, Kevin F. Tsai, Yu-Chin Hsu
Publisher: Kluwer Academic Pub
Publication Date: 1995-06-01
Language: English
Format: Hardcover
ISBN-10: 0792395972
ISBN-13: 9780792395973
Product ID: EPID399354
Portions of this page Copyright 1995 - 2009 Muze Inc. All rights reserved.
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Details
Publication Date:1995-06-01

Size
Length:356 pages
Height:9.8 in
Width:6.8 in
Thickness:1.0 in
Weight:28.8 oz

Industry Reviews
Intended for working professionals as well as students, this book introduces VHSIC Hardware Description Language (VHDL) and its use for synthesis. VHDL, a hardware description language which provides a means of specifying a digital system over different levels of abstraction, supports behavior specifications during the early stages of design process and structural specifications during later implementation stages. The first six chapters introduce the features of VHDL. Topics include a brief history of VHDL and how it is used in the design world; basic structures in VHDL; types, operators, and expressions; sequential statements; concurrent statements; and subprograms and packages. The second section (Chapters 7 to 14) discusses modeling at various levels of abstraction, the concept of synthesis, and how to write efficient VHDL design descriptions. Annotation copyright Book News, Inc. Portland, Or.
SciTech Book News (03/01/1996)

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